An Approach to Specification and Synthesis of Adaptive Interfaces of Reusable Hardware Modules

A novel methodology for specification and synthesis of adaptive interfaces for Soft IP cores using the VHDL+ extension to VHDL is presented . Our approach separates the specifications of IP core functional behaviour and core interface into different design units. While the core functional behaviour is defined in form of a VHDL+ model that has a transaction level interface, the core interface specification is captured in a distinct VHDL+ design unit, called the interface, and defines the module ports and the port signaling protocol. From a given VHDL+ specification of the IP core functional behaviour and the core interface, respectively, our tool MODIS generates a VHDL synthesis model of the IP core with an appropriate interface implementation. We demonstrate the applicability of our approach on a RT model of a simple CPU for which a serial and a PCI interface are specified and synthesized.